This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2002-231645, filed on Aug. 8, 2002, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor memory device and a method for testing a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having functions for processing external and internal accesses, and to a method for testing such a semiconductor memory device.
Electronic information devices incorporate semiconductor memory devices having large memory capacities (i.e., dynamic random access memory (DRAM)). A DRAM has a self-refreshing function to refresh the data of a memory cell in accordance with a counting operation performed by an internal circuit. The DRAM does not require an external device to perform refreshing. This decreases power consumption and simplifies the design of circuits in the periphery of the DRAM.
In a DRAM provided with the self-refreshing function, a timer of an internal circuit generates refresh requests (internal access) at predetermined time intervals. Further, a main controller of an external device generates write/read requests (external access) at certain timings. In other words, internal and external accesses are generated asynchronously. Accordingly, there is a demand for evaluating a DRAM having two asynchronous access modes.
FIG. 1 is a schematic block circuit diagram illustrating the input section of a prior art semiconductor memory device (DRAM) 50 provided with a self-refreshing function.
The DRAM 50 receives a plurality of control signals CTL and a plurality (only two bits shown in FIG. 1) of external address signals ADD via external terminals. The control signals CTL include a chip enable signal /CE, a write enable signal /WE, and an output enable signal /OE. The external address signals ADD include address signals A0 and A1. The signals /CE, /WE, /OE, A0, and A1 are input to a transition detection signal generation circuit 70 via input buffers 61, 62, 63, 64, and 65, respectively. The input buffers 61 to 65 function as initial input stage circuits, which convert an input signal to a signal having a level corresponding to the internal voltage of the device. Further, the input buffers 61 to 65 are each configured by a CMOS inverter or a C/M differential-amplifier.
The transition detection signal generation circuit 70 includes a plurality (five in FIG. 1) of transition detectors (TD) 71 to 75 and a pulse synthesizing circuit 76.
The transition detectors 71, 72, and 73 respectively detect the transition (transition between a high level and a low level) of the control signals CTL (/CE, /WE, and /OE) to generate input detection signals ceb, web, and oeb. The transition detectors 74 and 75 respectively detect the transition of the states (change of each bit) of the input external address signal ADD (A0 and A1) to generate address detection signals ad0 and ad1. The detection signals ceb, web, oeb, ad0, and ad1 are provided to the pulse synthesizing circuit 76.
The pulse synthesizing circuit 76 generates a transition detection signal mtd in accordance with the detection signals ceb, web, oeb, ad0, and ad1 and provides the transition detection signal mtd to a memory control circuit 77. In accordance with the transition detection signal mtd, the memory control circuit 77 generates a word line activation timing signal wl-timing to activate a word line of a memory cell. The word line of a memory cell corresponds to a predetermined read/write address, which is assigned by the external address signal ADD. The timing signal wl-timing is provided to a memory core 79.
A refresh timer 78 is connected to the memory control circuit 77. The refresh timer 78 generates a refresh request signal ref-req at predetermined time intervals and provides the refresh request signal ref-req to the memory control circuit 77. In accordance with the refresh request signal ref-req, the memory control circuit 77 generates a word line activation timing signal wl-timing to activate a word line of a memory cell. The word line of a memory cell corresponds to a predetermined refresh address, which is generated by an internal address counter (not shown).
The memory control circuit 77 further receives a test signal test from a test circuit (not shown) to conduct a test in a test mode in accordance with the test signal test.
FIG. 2 is a schematic block circuit diagram of the memory control circuit 77. The memory control circuit 77 includes a refresh determination circuit 81, an internal command generation circuit 82, and a timing generator 83.
The refresh determination circuit 81 receives the transition detection signal mtd, the refresh request signal ref-req, and the test signal test. In response to the refresh request signal ref-req, the refresh determination circuit 81 generates a refresh start signal ref-start, which starts refreshing (internal access), and a refresh state signal ref-state. The refresh start signal ref-start is provided to the timing generator 83, and the refresh state signal ref-state is provided to the internal command generation circuit 82.
When receiving the transition detection signal mtd before the refresh request signal ref-req, the refresh determination circuit 81 suspends refreshing and does not generate a refresh signal.
In this state, the refresh determination circuit 81 gives priority to read/write operations (external accesses) and starts refreshing after the read/write operations are completed. More specifically, after a read/write state signal rw-state, which is provided from the timing generator 83, is reset, the refresh determination circuit 81 generates the refresh start signal ref-start and the refresh state signal ref-state.
The refresh determination circuit 81 determines the input timings of the refresh request signal ref-req and the transition detection signal mtd, which are asynchronously input, and determines which one of the refreshing operation and the read/write operation has priority when there is more than one access.
In response to the transition detection signal mtd, the internal command generation circuit 82 generates the read/write start signal rw-start, which starts read/write operations, and provides the read/write start signal rw-start to the timing generator 83. When the internal command generation circuit 82 receives the refresh state signal ref-state, the internal command generation circuit 82 provides the read/write start signal rw-start to the timing generator 83 after the refresh state signal ref-state is reset.
The timing generator 83 receives the refresh start signal ref-start and the read/write start signal rw-start. In response to the refresh start signal ref-start, the timing generator 83 generates the word-line activation timing signal wl-timing in correspondence with the refresh address. In response to the read/write start signal rw-start, the timing generator 83 generates the read/write state signal rw-state and generates the word-line activation timing signal wl-timing in correspondence with the predetermined read/write address.
In addition to the word line activation timing signal wl-timing, the timing generator 83 generates other internal operation signals, such as a sense amplifier activation timing signal for activating a sense amplifier. Only the word line activation timing signal wl-timing will be discussed below.
The operation of the DRAM 50 will now be discussed. FIG. 3 is a waveform diagram illustrating the operation of the transition detection signal generation circuit 70.
For example, when the chip enable signal /CE goes low, the transition detector 71 generates the input detection signal ceb (pulse signal). The pulse synthesizing circuit 76 generates the transition detection signal mtd in accordance with the transition signal mtd. Then, for example, when the address signal A0 goes high (1), the transition detector 74 generates an address detection signal ad0 (pulse signal). In accordance with the detection signal ad0, the pulse synthesizing circuit 76 generates the transition detection signal mtd.
In the transition detection signal generation circuit 70, the pulse synthesizing circuit 76 generates the transition detection signal mtd when a transition occurs in any one of the control signals (/CE, /WE, and /OE) and the address signals ADD (A0 and A1).
FIGS. 4 and 5 are waveform charts illustrating the operation of the memory control circuit 77. FIG. 4 illustrates an example in which there is more than one access at the same time and the transition detection signal mtd is provided to the memory control circuit 77 before the refresh request signal ref-req.
Among the control signal CTL and the external address signal ADD, the pulse synthesizing circuit 76 detects the signal that has undergone a transition (i.e., shifting of levels between high and low) and generates the transition detection signal mtd. Then, the refresh timer 78 generates the refresh request signal ref-req. Thus, the refresh operation is performed after the read/write operation.
More specifically, the internal command generation circuit 82 generates the read/write start signal rw-start in accordance with the transition detection signal mtd. The timing generator 83 generates the read/write state signal rw-state and the word line activation timing signal wl-timing in accordance with the read/write start signal rw-start. In this state, a word line corresponding to the predetermined read/write address is activated to read or write cell data.
When the read/write operation is completed and the read/write state signal rw-state is reset, the refresh determination circuit 81 generates the refresh start signal ref-start and the refresh state signal ref-state. In accordance with the refresh start signal ref-start, the timing generator 83 generates the word line activation timing signal wl-timing. This activates the word line corresponding to a predetermined refresh address and refreshes the cell data.
FIG. 5 illustrates an example in which the refresh request signal ref-req is provided to the memory control circuit 77 before the transition detection signal mtd. Contrary to the operations illustrated in FIG. 4, the read/write operation is performed after the refresh operation.
The refresh determination circuit 81 generates the refresh start signal ref-start and the refresh state signal ref-state in accordance with the refresh request signal ref-req. The timing generator 83 generates the word line activation timing signal wl-timing in accordance with the refresh start signal ref-start. This activates the word line corresponding to a predetermined refresh address and refreshes the cell data.
When the refresh operation is completed and the refresh state signal ref-state is reset, the internal command generation circuit 82 generates the read/write start signal rw-start in response to the transition detection signal mtd. In accordance with the read/write start signal rw-start, the timing generator 83 generates the read/write state signal rw-state and the word line activation timing signal wl-timing. In this state, the reading or writing of the cell data is performed.
When there is more than one access at the same time and the read/write operation (external access) is performed after the refreshing operation (internal access), the speed of the read/write operation becomes slowest. That is, the external access time becomes longest. Thus, to evaluate the characteristics of the DRAM 50, which has two access modes (i.e., external access mode and internal access mode), the operation pattern when the external access time becomes maximum (i.e., worst pattern) must be checked.
FIG. 6 is a waveform chart illustrating a test mode. More specifically, FIG. 6 is a waveform chart simulating an operation pattern when a read/write operation is performed after a refresh operation.
In the test mode, the refresh determination circuit 81 receives a test signal test from a test circuit (not shown). When the refresh determination circuit 81 receives the test signal test, the refresh determination circuit 81 generates the refresh start signal ref-start in accordance with the transition detection signal mtd.
The refresh determination circuit 81 asynchronously receives the refresh request signal ref-req and the transition detection signal mtd. Thus, when performing refreshing in response to the refresh request signal ref-req during the test mode, the desired operation pattern is not repeated. Accordingly, in the test mode, the refresh determination circuit 81 generates the refresh start signal ref-start and the refresh state signal ref-state in accordance with the transition detection signal mtd. When the refresh operation is completed and the refresh state signal ref-state is reset, the internal command generation circuit 82 generates the read/write start signal rw-start in accordance with the transition detection signal mtd.
In the test mode, using the generation of the transition detection signal mtd as a trigger, the refresh operation is started to simulate and reproduce the worst pattern so that the external access time can be measured to evaluate the read/write operation.
However, the prior art DRAM 50 has the problems described below.
[1: Problem When Detecting a Deficient Mode]
One problem (deficient mode) of the DRAM 50, for example, when there are successive external accesses, is an operation delay in the device (resulting from process fluctuation, temperature fluctuation, or insufficient voltage margin) that prolongs the cycle length. As a result, the DRAM 50 may not be able to shift to the read/write operation for the next cycle.
FIG. 7 is a waveform chart illustrating such a deficient mode. FIG. 7 illustrates an example in which the transition detection signal mtd is generated when the chip enable signal /CE goes low, the output enable signal /OE goes high, or the address signal ADD (A0 and A1) changes.
When the chip enable signal /CE goes low, the transition detection signal mtd is generated. In accordance with the transition detection signal mtd, the read/write start signal rw-start and the read/write state signal rw-state are generated. This performs the read/write operation.
Then, when the output enable signal /OE goes high, the transition detection signal mtd is generated. In this state, for example, when there is an operation delay in the device, the next cycle cannot be entered. Thus, the read/write start signal rw-start and the read/write state signal rw-state are not generated (the broken lines in FIG. 7 illustrate normal operation).
When there is a deficient mode such as in FIG. 7 and if the address signal ADD changes after the output enable signal /OE goes high as shown in FIG. 8, the read/write start signal rw-start and the read/write state signal rw-state are generated in accordance with the transition detection signal mtd.
In this case, since the read/write operation is started, a deficiency may not be detected even if there actually is a deficient mode. Thus, device evaluation cannot be performed accurately in the prior art.
[Deficiency Related With Test Mode]
In the test mode, the refresh start signal ref-start is generated in accordance with the transition detection signal mtd to start the refresh operation. Thus, during the test mode, a test in the desired operation pattern may not be performed since the refresh operation is not performed during the normal mode.
FIG. 9 is a waveform diagram illustrating an example of an operation pattern during the normal mode. FIG. 9 shows the operation pattern when there is an external request for the write operation and an internal request for the refresh operation and the refresh operation is performed first (worst pattern). In this example, the transition detection signal mtd is generated when the chip enable signal /CE goes low and the write enable signal /WE goes high. In the example of FIG. 9, the write operation is performed when the chip enable signal /CE goes low.
FIG. 10 is a waveform diagram illustrating an example in which the operation pattern of FIG. 9 is performed in the test mode.
In the example of FIG. 10, the transition detection signal mtd is generated when the chip enable signal /CE goes low. The refresh start signal ref-start is generated and the refresh operation is started in accordance with the transition detection signal mtd. When the refresh operation is completed, the read/write start signal rw-start (more specifically, write start signal) is generated and the write operation is started in accordance with the transition detection signal mtd.
Subsequent to the completion of the write operation, when the write enable signal /WE goes high and the transition detection signal mtd is generated in accordance with the write enable signal /WE, the refresh operation is performed for the second time in accordance with the transition detection signal mtd. Accordingly, in the prior art test mode, since the second refresh operation is performed unintentionally, the operation pattern in the normal mode of FIG. 9 cannot be reproduced.
FIG. 11 is a waveform diagram illustrating an example of a further operation pattern in the normal mode. FIG. 11 shows an operation pattern when there are requests for the write operation and the refresh operation at the same time, and the read operation is performed after the write operation. In this example, the transition detection signal mtd is generated when the chip enable signal /CE goes low, the write enable signal /WE goes high, and the output enable signal /OE goes high (not shown). In the example of FIG. 11, the write operation is started when the chip enable signal /CE goes low, and the read operation is started when the output enable signal /OE goes low.
FIG. 12 is a waveform chart illustrating an example when the operation of FIG. 11 is performed in the test mode. The transition detection signal mtd is generated when the chip enable signal /CE goes low. The refresh start signal ref-start is generated and the refresh operation is started in accordance with the signal mtd. When the refresh operation is completed, the read/write start signal rw-start (more specifically, write start signal) is generated and the write operation is started in accordance with the transition detection signal mtd, which functions as a trigger for starting the refresh operation.
Subsequent to the completion of the write operation, when the write enable signal /WE goes high, the transition detection signal mtd is generated in accordance with the write enable signal /WE. The refresh operation is performed for the second time when the refresh start signal ref-start is generated in accordance with the transition detection signal mtd. When the refresh operation is completed, the read/write start signal rw-start (more specifically, read start signal) is generated in accordance with the transition detection signal mtd, which is the trigger of the second refresh operation, to start the read operation.
Accordingly, in the example of FIG. 12, since the second refresh operation is performed unintentionally, the operation pattern in the normal mode of FIG. 11 cannot be reproduced in the test mode.
In the prior art, when an unintentional refresh operation is performed during the test mode, the characteristic evaluation is conducted with an operation pattern differing from the actual pattern. Thus, the device cannot be properly evaluated. When the test mode is performed, power draw increases since an unnecessary refresh operation is performed. Therefore, in accordance with the test result, the guaranteed operation may be over-evaluated or normal functioning may be erroneously determined as abnormal functioning. In other words, in the prior art, the testing cannot be performed with the intended operation pattern, and the device evaluation cannot be performed properly.
One aspect of the present invention is a semiconductor memory device including first and second access modes and an entry signal generation circuit for logically synthesizing a plurality of input signals to generate a first entry signal used to enter the first access mode. A control circuit is connected to the entry signal generation circuit to generate a first mode trigger signal in response to the first entry signal. When the control circuit receives a second entry signal to enter the second access mode, the control circuit generates a second mode trigger signal in response to the second entry signal. The entry signal generation circuit logically synthesizes the input signals in a selective manner in accordance with a selection control signal to generate the first entry signal.
A further aspect of the present invention is a semiconductor memory device including first and second access modes and an entry signal generation circuit for logically synthesizing a plurality of input signals to generate an entry signal used to enter the first access mode or the second access mode. A control circuit is connected to the entry signal generation circuit to generate a first mode trigger signal, which is used to start the first access mode, in response to the entry signal and to generate a second mode trigger signal, which is used to start the second access mode, in response to the entry signal. The entry signal generation circuit logically synthesizes the input signals in a selective manner in accordance with a predetermined selection control signal to inhibit the generation of the entry signal.
A further aspect of the present invention is a semiconductor memory device including first and second access modes and an entry signal generation circuit for logically synthesizing a plurality of input signals to generate a first entry signal used to enter the first access mode and a second entry signal used to enter the second access mode. A control circuit is connected to the entry signal generation circuit to generate a first mode trigger signal, which is used to start the first access mode, in response to the first entry signal and to generate a second mode trigger signal, which is used to start the second access mode, in response to the second entry signal. The entry signal generation circuit logically synthesizes the input signals in a selective manner in accordance with a predetermined selection control signal to inhibit the generation of the first entry signal or the second entry signal.
A further aspect of the present invention is a method for testing a semiconductor memory device having a first access mode, a second access mode, and a test mode. The method includes receiving a test signal to enter the test mode, receiving a plurality of input signals, selecting at least one of the input signals and detecting transition of the selected at least one of the input signals, and starting one of the access modes in accordance with the transition detection of the selected at least one of the input signals.
A further aspect of the present invention is a method for testing a semiconductor memory device having a first access mode and a second access mode. The method includes receiving a plurality of input signals, logically synthesizing the input signals to generate an entry signal used to enter the first access mode or the second access mode, logically synthesizing the input signals in a selective manner in accordance with the selection control signal to inhibit the generation of the entry signal.
A further aspect of the present invention is a method for testing a semiconductor memory device having a first access mode and a second access mode. The method includes receiving a plurality of input signals, logically synthesizing the input signals to generate a first entry signal used to enter the first access mode, logically synthesizing the input signals to generate a second entry signal used to enter the second access mode, and logically synthesizing the input signals in a selective manner in accordance with the selection control signal to inhibit the generation of the first entry signal or the second entry signal.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.